The workshop on Computer Vision on Low-Power Reconfigurable Architectures will be held as part of the 21st International Conference on Field Programmable Logic and Applications in Chania, Crete, Greece

Workshop Proceedings

The full workshop proceedings are available here.

Scope and Topics

In the past decade the field of computer vision has grown significantly in research, development and applications. Computer vision is used in various domains ranging from object recognition, robotics, and scene reconstruction to automation and interaction. The general superiority of visual information in diversity and reliability over other sensors' is more apparent than ever.

As sensor technology continues to improve, image resolutions increase at growing frame rates. In order to achieve real-time video processing, suitable processing platforms are required which provide the required processing performance while keeping power consumption low. Today's pursuit of highly capable and long lasting battery-powered mobile systems and devices puts tight constraints on energy consumption and device size.

Research in computer vision as well as video and image processing has mainly focused on elevating the functionalities while little attention has been paid to power-aware computation. For the application of cutting-edge computer vision methods in real world systems and industrial applications it is essential to migrate from powerful workstations towards embedded processors and enforce the associated shift in application development and implementation.

The objective of this workshop is to examine the state of the art in the application of reconfigurable devices in computer vision applications. In particular the potential of low-power, energy-efficient FPGAs, GPGPUs and many-cores in the context of computer vision applications is of interest. We aim to bring together the leading researchers and developers from academia and industry in order to facilitate the exchange of ideas and experiences from research and real-world applications and to discuss future directions.

List of Topics


Workshop Format

The structure of the workshop will consist of a small number of talks and significant time for the group discussions amongst the attendees in the context of presented posters. We explicitly solicit the presentation of demonstrators and demonstrations where appropriate and practicable. It will be an excellent opportunity for extended interactions with other researchers on this important topic.


Preliminary Program

Chair: Dr Markus Koester, Paderborn University, Germany

13:00 - 14:00 Invited talk, title TBA
Kevin M. Irick, Microsystems Design Laboratory, Pennsylvania State University, USA
14:00 - 14:30 Hardware Accelerated object Tracking
Tobias Becker, Qiang Liu, Wayne Luk, Georg Nebehay and Roman Pflugfelder
14:30 - 15:00 Single Low-Power FPGA Implementation of Moving Object Detection
Tomasz Kryjak, Mateusz Komorkiewicz and Marek Gorgon
15:00 - 16:00 Poster and Demo Session
(Coffee and Tea will be served during the poster and demo session)
16:00 - 17:00 Invited talk, title TBA
Ram K. Krishnamurthy, High Performance & Low Voltage Circuits Research Group, Intel Labs, USA
17:00 - 17:30 A Hybrid Multi-Core Architecture for Real-Time Video Tracking
Markus Happe and Enno Lubbers
17:30 - 18:00 A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC
Daniel Ziener, Stefan Wildermann, Andreas Oetken, Andreas Weichslgartner and Jurgen Teich
18:00 Closing remarks


Invited Talks

Invited talk, title TBA
Kevin M. Irick, Microsystems Design Laboratory, Pennsylvania State University, USA

Abstract: Recent advances in chip fabrication have allowed the integration of specialized DSP units, abundant on-chip memories, and embedded processor cores within a single reconfigurable FPGA device. Consequently, FPGAs have outgrown their elementary roles as logic-level converters and configurable address decoders. In fact, FPGAs have become the leading performers for accelerating many complex signal and image processing applications. In the context of Size, Weight, and Power (SWaP) constraints, there are clear advantages of utilizing FPGA technology as compared to competing platforms such as Multi-Core and GPGPU.
However, the difficulties associated with utilizing FPGA technology have created a need for design methodologies that ease the composition of systems - making the process accessible to those working at the algorithm, application, and system levels. This talk will give an overview of our solutions to automating and accelerating the composition of image processing systems on diverse FPGA computing platforms. Moreover, the talk will present our recent and exciting experiences in realizing cutting-edge, bio-inspired Neuromorphic vision systems. Finally, we give our perspective on next generation reconfigurable computing platforms and the requirements they must fulfill to remain impactful in future high-performance vision applications.

Bio: Kevin Irick received the BS degree in Electronics Engineering Technology from DeVry University in 2002. He earned the MS and PhD degrees in Computer Science and Engineering from The Pennsylvania State University in 2006 and 2009 respectively. Currently, he is a Research Scientist in the Microsystems Design Lab in the Department of Computer Science and Engineering at Penn State. Irick currently leads a team of four graduate students and two post-doctorates in a project focused on using FPGAs to realize bio-inspired vision systems. His research interests include application-specific hardware accelerators, hardware-assisted image processing and recognition, and high-performance computing on FPGAs.

Invited talk: High Performance Energy Efficient Reconfigurable Accelerators for the Sub-45nm Era
Ram K. Krishnamurthy, High Performance & Low Voltage Circuits Research Group, Intel Labs, USA

Abstract: With the emergence of high-performance multi-core microprocessors in the sub-45nm technology era, special-purpose hardware accelerator engines embedded within the core architecture have the potential to achieve 10-100X increase in energy efficiency across a wide domain of compute-intensive video/graphics processing, computer vision/recognition algorithms and scientific workloads. In this talk, we present multi-core microprocessors integrated with on-die energy-efficient reconfigurable accelerators and co-processor engines to achieve well beyond tera-scale performance in sub-45nm technologies. Recent trends and challenges in multi-core microprocessors will be presented, followed by key enablers for reconfigurability of specialized hardware engines to support multiple protocols while substantially improving time-to-market and amortizing die area cost across a wide range of compute workloads and functions. Specific design examples and case studies supported by silicon measurements will be presented to demonstrate reconfigurable engines for SIMD graphics vector processing and fine-grain configurable logic fabrics. Power efficient optimizations of reconfigurable processors to support fine-grain power management, dynamic on-the-fly configurability and ultra-low voltage scalability will also be described.

Bio: Ram K. Krishnamurthy is a Senior Principal Engineer with Circuits and Systems Research, Intel Labs in Hillsboro, OR, where he heads the high-performance and low-voltage circuits research group. He received the B.E. degree in Electrical Engineering from Regional Engineering College, Trichy, India, in 1993, and the Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh, PA, in 1998. He has been with Intel Corporation since 1998. He holds 90 issued patents and has published over 100 conference/journal papers and 3 book chapters on high-performance energy-efficient microprocessor design. He serves as Intel's representative on the SRC Integrated Circuits and Systems Sciences Task Force, has been a guest editor of the IEEE Journal of Solid-State Circuits and on the technical program committees of the ISSCC, CICC, and SOCC conferences. He served as the Technical Program Chair/General Chair for the 2005/2006 IEEE International Systems-on-Chip Conference and presently serves on the conference's steering committee. Krishnamurthy has served as an adjunct faculty of the Electrical and Computer Engineering department at Oregon State University, where he taught advanced VLSI design. He has received two Intel Achievement Awards, in 2004 and 2008, for the development and technology transfer of novel high-performance execution core arithmetic circuits and special-purpose hardware encryption accelerators. He is a Fellow of the IEEE.



We invite contributions to the workshop in the form of 2-page abstracts in FPL2011 style, to be presented at the workshop as posters. Authors of the best contributions will be invited to give an oral presentation of their work.

Accepted abstracts will be published on the FPL 2011 website and will be included on the CD along the proceedings of the FPL conference.

We strongly encourage the use of LaTeX for the preparation of the abstract.

Deadline for Submission: (31 May 2011) 6 June 2011

Notification of Acceptance: (15 June 2011) 20 June 2011

Notification of Acceptance: 15 June 2011

Submissions should be made by sending a 2-page PDF file to fpl2011 [at] cit-ec [dot] uni-bielefeld [dot] de.



Markus Koester, University of Paderborn, Germany

Felix Werner, Bielefeld University, Germany



fpl2011 [at] cit-ec [dot] uni-bielefeld [dot] de